A successive approximation register (SAR) analog-to-digital converter (ADC) is commonly used for low-power, medium-to-high-resolution applications when sampling rates are below a few mega-samples per second.
Despite SAR ADC devices utilize very little amount of power, a conventional SAR ADC device still exhibit multiple drawbacks. One of the drawbacks is a need to have a large capacitor formed within a digital-to-analog converter (DAC) circuit, which is a component within the SAR ADC device. Furthermore, the area of DAC circuit is generally proportional to the SAR ADC device resolution. Therefore, a fine resolution SAR ADC may have a significantly large in size DAC circuit. This is highly undesirable when the SAR ADC device is implemented on a silicon device.
In addition, conventional switching schemes that are available on conventional SAR ADC devices may not be energy-efficient. Furthermore, most of the switching schemes that are developed for a differential structure are generally not compatible for a single-ended structure.
The conventional single-ended SAR ADC devices may also suffer from problems such as comparator offset, comparator kick-back noise, and need for an additional/external circuit to generate a common mode voltage.
It is within this context that the embodiments described herein arise.